This invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
A wide variety of semiconductor devices have been used in an integrated circuit and a large scale integrated (LSI) circuit. Among others, a dynamic random access memory (will be abbreviated to DRAM hereinafter) will be well known in the art as a read-write random access memory and has been specified by storage cells each of which is a combination of a single transfer transistor and a single capacitor. In this connection, each storage cell of the DRAM is simple in structure and is adequate for high integration of the semiconductor device.
In such a storage cell of the DRAM, recent development has been directed to a capacitor which has a three-dimensional structure, so as to integrate the DRAM at a more high density. This is because such a three dimensional structure of the capacitor enables a reduction of an area occupied by the capacitor and a fine structure of the capacitor. At any rate, such a capacitor of a three-dimensional structure may be called a three-dimensional capacitor and has a lower electrode, an upper electrode, and an insulator film interposed between the lower and the upper electrodes. The lower and the upper electrodes will be generalized as first and second electrodes, respectively, while the insulator will be called a capacitive insulator film, respectively. In addition, the lower or the first electrode will be often referred to as a storage electrode.
In the meanwhile, the three-dimensional capacitor should have capacitance greater than predetermined capacitance in order to insure stability in operation of the DRAM and reliability thereof. Under the circumstances, consideration has been made about widening a surface area of the lower or the first electrode included in the three-dimensional capacitor.
Herein, it is to be noted that the three-dimensional capacitor is classified into a capacitor of a trench type and a capacitor of a stacked type both of which will be simply referred to as a trench capacitor and a stacked capacitor, respectively. Although the trench capacitor and the stacked capacitor have merits and demerits, respectively, the staked capacitor excels the trench capacitor in a property of resistance against an alpha ray and a noise generated by other circuits and in stability of operation in small capacitance. Accordingly, it has been expected that the stacked capacitor is more effective than the trench capacitor in a DRAM of 1 Gb which requires a design standard of 0.15 micron meter or so.
As such a stacked capacitor, a lot of proposals have been recently made about a fin structure and a cylinder structure.
For example, the stacked capacitor of the fin structure has been disclosed in Japanese Unexamined Patent Publication No. Hei 5-82750, namely, 82,750/1993 which will be referred as a first reference. In the stacked capacitor disclosed, a lower or a first electrode is shaped into a fin structure which has a plurality of fins spaced apart from one another. The plurality of the fins are connected to a stem portion contacted with a semiconductor substrate and horizontally extended from the stem portion over the semiconductor substrate with gaps left therebetween. In other words, the illustrated lower electrode of the stacked capacitor looks in section like a tree which has a stem and a plurality of branches extended from the stem.
The stacked capacitor of the this type is disadvantageous in that the fins or branches become weak in mechanical strength and are sagged or deformed as each fin becomes thin in thickness.
On the other hand, a stacked capacitor of the cylinder structure has been proposed in Japanese Unexamined Patent Publication No. Hei 4-264,767, namely, 264767/1992 which may be named a second reference. In the stacked capacitor illustrated in the second reference, a lower electrode has a multi-cylindrical structure formed by a plurality of upright cylinders which concentrically stand up from a semiconductor substrate with gaps left between two adjacent ones of the upright cylinders. The multi-cylindrical structure looks like a plurality of walls concentrically which stand on the semiconductor substrate with gaps left between two adjacent ones of the walls.
In this event, it is preferable that each cylinder or wall is thin in thickness to achieve high integration and high capacitance. However, such a thin wall becomes weak in mechanical strength. Moreover, a new material which has a weak stress and a good step coverage characteristic should be developed to enable thin cylinders. Under the circumstances, restrictions are imposed also on an increase of capacitance by increasing the cylinders.
In the interim, a flat area of a single cell becomes narrow with an increase of a memory capacity of the DRAM. However, capacity of each capacitor should be kept substantially constant even on an increase of the memory capacity in order to prevent a soft error resulting from an irradiation of the alpha ray. Taking this into account, the stacked capacitor should become high when the fin structure of the first reference is adopted. However, a level difference becomes large between an array portion of the memory cell and a peripheral portion. This brings about degradation of resolution in a photolithography process and a breakage or shortening of wirings.